14. Coprocessor 0

14.20 Performance Counter Registers (25)

The R10000 processor defines two performance counters and two associated control registers, which are mapped into CP0 register 25. An encoding in the MTC0/MFC0 instructions on register 25 indicates which counter or control register is used.

Each counter is a 32-bit read/write register and is incremented by one each time the countable event, specified in its associated control register, occurs. Each counter can independently count one type of event at a time.

The counter asserts an interrupt, IP[7], when its most significant bit (bit 31) becomes one (the counter overflows) and the associated performance control register enables the interrupt.

The counting continues after counter overflow whether or not an interrupt is signalled.

The format of the control registers are shown in Figure 14-22.

Figure 14-22 Control Register Format

The fields of the Control register are:

The Event field specifies the event to be counted, listed in Table 14-18.

Table 14-18 Counter Events

Footnote to Table 14-18. (See page 248 in Errata.)

The IE bit enables the assertion of IP[7] when the associated counter overflows.
The U, S, K, and EXL bits indicate the processor modes in which the event is counted: U is user mode; S is supervisor mode; K is kernel mode when EXL and ERL both are set to 0; the system is in kernel mode and handling an exception when EXL is set to 1, as shown in Table 14-22.

0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)

These modes can be set individually; for example, one could set all four bits to count a certain event in all processor modes except during a cache error exception.

The following rules apply:

R10000 defines "issue" as the point in time that an instruction becomes active and is issued to a functional unit for execution.
R10000 defines "graduation" as the point in time that the functional unit successfully completes the execution of an instruction. It is the oldest active instruction.
The number of executed branches is the difference between decoded branches and mispredicted branches. Although newer branches may be speculatively decoded before an older branch is resolved as mispredicted, these newer branch instructions, nullified by the older misprediction, are not counted as mispredicted.
When an integer multiply or divide instruction graduates, it is counted as two graduated instructions.
Any instruction that sets the FP Status register bits (EVZOUI) is counted as a graduated floating point instruction.
TLB misses are counted as either nascent or within the TLB handler.

The performance counters and associated control registers are written by using an MTC0 instruction, as shown in Table 14-19.

Table 14-19 Writing Performance Registers Using MTC0

The performance counters and associated control registers are read by using a MFC0 instruction, as shown in Table 14-20.

Table 14-20 Reading Performance Registers Using MFC0

The format of the performance control registers are shown in Table 14-21.

Table 14-21 Performance Control Register Format

The count enable field specifies whether counting is to be enabled during User, Supervisor, Kernel, and/or Exception level mode. Any combination of count enable bits may be asserted.

All unused bits in the performance control registers are reserved.

All counting is disabled when the ERL bit of the CP0 Status register is asserted.

Table 14-22 defines the operation of the count enable bits of the performance control registers.

Table 14-22 Count Enable Bit Definition

The following rules apply:

The performance counter registers may be preloaded with an MTC0 instruction, and counting is enabled by asserting one or more of the count enable bits in the performance control registers.
The interrupt enable bit must be asserted to cause IP[7].
To determine the cause of the interrupt, the interrupt handler routine must query the following:
- the performance counter register
- the interrupt enable bit of the associated performance control register of both counters
If neither of the counters caused the interrupt, IP[7] must be the result of the CP0 Count register matching the CP0 Compare register.

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